Search results for "Analog-to-Digital converter"
showing 7 items of 7 documents
Silicon dosimeters based on Floating Gate Sensor: design, implementation and characterization
2020
A rad-hard monolithic dosimeter has been implemented and characterized in a standard 180 nm CMOS technology. The radiation sensor (C-sensor) is based on a Floating Gate (FG) MOS discharge principle. The output current is processed by a current-to-voltage (I/V) interface and then converted by a 5-bit flash ADC. The dosimeter is re-usable (FG can be recharged) and can detect a dose up to 1krad (Si) with a resolution of 30rad (Si) typical over temperature 0 to 85°C range. The ADC allows easy further signal processing for calibration and averaging, etc. The power consumption of C-sensor plus I/V interface is < 2mW from a 5 V power supply. The overall layout area is less than 0.25mm2. The Rad…
Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs
2019
Abstract A low-complexity post-processing algorithm to estimate and compensate for timing skew error in a four-channel time-interleaved analog to digital converter (TIADC) is presented in this paper, together with its hardware implementation. The Lagrange interpolator is used as the reconstruction filter which alleviates online interpolator redesign by using a simplified representation of coefficients. Simulation results show that the proposed algorithm can suppress error tones for input signal frequency from 0 to 0.4 f s . The proposed structure has, at least, 41% reduction in the number of required multipliers. Implementation of the algorithm, for a four-channel 10-bit TIADC, show that, f…
Performance of the front-end electronics of the ANTARES neutrino telescope
2010
ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named Analogue Ring Samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the fu…
Performance of the upgraded PreProcessor of the ATLAS Level-1 Calorimeter Trigger
2020
The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the newMultichip Modules along with the improvements to the signal processing achieved.
Digitaler Spektrumstabilisator für schnelle Analog-Digital-Konverter
1969
Abstract A versatile spectrum stabilizer is described, suitable for all ADC's with a digital parallel output and a pilot pulse at the end of the conversion. The stabilizer is especially developed for a 100 MHz ADC, but it is independent of the digitizing rate and the mode of conversion. The unit has a maximum cyclus time of 2 μsec and permits a parallel transfer rate of 500 kHz. The stabilizer corrects the effects of gain drift and is insensitive to statistical errors.
Wide bandwidth impedance meter using low rate random sampling
2008
A novel impedance measurement method based on random sampling of voltage and current signals is proposed. This technique dramatically reduces the sampling frequency requirements, thus circumventing the limitations imposed by maximum speed of the analog to digital converter and the signal processing unit. The lowering of the sampling frequencies allows the design and the implementation of an almost all digital architecture by using a simple microprocessor based embedded system and a digital frequency synthesizer. The basic principles are presented, and the implemented algorithms are described. Experimental results show the instrument performances compared to others commercial alternatives.
Calibration of the underground muon detector of the Pierre Auger Observatory
2021
To obtain direct measurements of the muon content of extensive air showers with energy above $10^{16.5}$ eV, the Pierre Auger Observatory is currently being equipped with an underground muon detector (UMD), consisting of 219 10 $\mathrm{m^2}$-modules, each segmented into 64 scintillators coupled to silicon photomultipliers (SiPMs). Direct access to the shower muon content allows for the study of both of the composition of primary cosmic rays and of high-energy hadronic interactions in the forward direction. As the muon density can vary between tens of muons per m$^2$ close to the intersection of the shower axis with the ground to much less than one per m$^2$ when far away, the necessary bro…